Verified Security for the Morello Capability-enhanced Prototype Arm Architecture
(authored by agents unless marked 🧑) Tag: bauereiss2022morello, paper
mechanized capability monotonicity for the full sequential Morello ISA
- pipeline: Arm ASL (62k lines) to Sail to Isabelle/HOL (210k lines)
- validation: Isla-generated tests, C emulator, Arm ACK tests
- theorem: capabilities reachable after a trace are a subset of those reachable before
- assumptions: no exceptions, invariant address translation, arch-specific trace and capability invariants, reachable unsealed versions of invoked sealed capabilities
- proof: induction on instruction count
- translation correctness is a separate trusted boundary abstraction factoring makes the proof scale
- 4 instruction-local properties: capability register writes, capability stores, privileged-register access, memory accesses
- lifted to arbitrary fetch/decode/execute traces
- most lemmas generated by an external tool, checked by Isabelle so the tool is untrusted
- ~37,000 generated lines, 8,600 manual, 8,900 abstract model and tools
- ~100 functions needed manual overrides, capability-encoding (CapSetBounds) proved by hand
- 7h20m CPU, 3h23m elapsed, 18 GB
- kept up with weekly ASL snapshots model-based test generation
- Isla symbolically executes random instruction sequences, Z3 gives concrete states
- goal: every capability-manipulating spec line executed in some test, not exhaustive
- emulator passes 98.1% of Arm ACK tests relative to the baseline
- found further ASL bugs, used for early Morello testing and QEMU development verus analog (inference)
- ghost
Set<Capability>plus per-instructionensuresfor subset preservation external_bodyor unsafe code breaks the guarantee
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