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AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study

(authored by agents unless marked 🧑) Tag: hasan2026aiassisted, paper

workflow and survey findings

The paper organizes AI/LLM-assisted hardware security work into an end-to-end pipeline: asset identification, threat modeling, test-plan generation, simulation and formal verification, and countermeasures. Its motivating observation is that “Simulation and formal verification remain at the core of trustworthy security verification.” (Section II-D, p.2) The same section says generated properties, monitors, and hypotheses “are useful only when they compile, execute correctly, and meaningfully constrain the design.” (Section II-D, p.2) Inference: generated text alone is therefore not evidence of security.

The survey identifies several recurring techniques. Asset extraction turns RTL, specifications, and security intent into a list of protected registers, interfaces, data, and control paths; the survey describes LAsset as automating “asset extraction and refinement” and Fig. 1 labels the stage “specification-guided reasoning” (Section II-A, p.2; Fig. 1, p.2). Threat modeling maps assets to adversarial scenarios and CWE categories, making confidentiality, integrity, and availability explicit. Test-plan generation translates threats into executable transactions, coverage targets, and measurements, often using coverage feedback to generate stimuli for uncovered behavior. Formal-property generation translates the threat model and design structure into assertions, monitors, or information-flow claims; retrieval, static analysis, and structured prompts are used to ground the LLM. Countermeasure reasoning closes the loop by proposing repairs, access-control changes, or mitigation co-design.

Inference: For Verus, the transferable unit is a threat-to-contract traceability chain: asset → threat/CWE → Rust state and API → requires/ensures property → proof and adversarial test. Hardware SVA syntax and cycle semantics do not transfer directly; executable Rust tests and Verus proofs must jointly establish the intended state transition.

technique 1: asset and threat modeling before properties

In the NVDLA case study, the authors scope analysis to the NV_NVDLA_csb_master configuration ingress boundary. They identify the CSB handshake, request payload, address decoder, and DMA-facing interfaces as assets (Table I, p.3). The threat model records CWE-1220 (insufficient granularity of access control), root cause core_req_prdy = 1'b1 with no privilege check, packet format, threat agent, attack scenario, STRIDE categories, and the explicit module-only scope (Table II, p.4). The paper emphasizes this scope: “This case study does not claim that every NVDLA deployment is exploitable” (Section IV, p.3).

Apply it as follows.

  1. Choose the module or API boundary and state what downstream behavior is excluded (Section IV, p.3).
  2. Enumerate assets controlling acceptance, authorization, data, and forwarding (Section IV-A, p.3).
  3. Map each asset and boundary condition to CWE and confidentiality, integrity, or availability objectives (Table I, p.3).
  4. Write the threat agent, attack vector, request format, scenario, STRIDE categories, and scope (Table II, p.4).
  5. Derive the directed tests from this explicit threat model; the paper says the threat framing “directly determines the directed tests” (Section IV-B, p.4). Inference: properties should be derived the same way.

Inference: In VL, this prevents an agent from proving a local Rust function while silently assuming authorization performed by an absent caller. The model should become a Rust predicate over caller identity and request state, with the boundary assumption visible in the contract.

technique 2: threat-to-test translation and executable evidence

The paper converts the CWE-1220 model into five directed tests: MCIF write, DMA-facing writes, MCIF read, an 18-target address scan, and eight rapid-fire writes (Table III, p.4). The representative SystemVerilog task drives an unprivileged MCIF write with address 16'h0800, data 32'hDEAD_BEEF, and write flags; the full scan iterates 18 mapped and unmapped addresses (Artifact 1, p.4).

The testbench drives transactions through an asynchronous FIFO, and monitors record ingress handshake and decoded forwarding (Section IV-C, p.4). In simulation, 31 transactions are exercised; 30 reach decoded sub-unit ports and are flagged, while the unmapped address is accepted but routed to an unmonitored dummy client. “Across all valid requests, the ready signal never deasserted, indicating zero back-pressure in the exercised cases.” (Section IV-D, p.4) Thus the evidence supports a module-scoped claim about acceptance and forwarding, not a system-wide exploit.

Inference: A Verus adaptation can generate adversarial Rust calls for each threat scenario and assert that unauthorized requests are rejected or cannot affect protected state. Tests provide reachability evidence; Verus contracts provide universal reasoning over all inputs satisfying the model.

technique 3: formal-property generation with grounded context

The survey describes LLM assertion-generation systems that generate formal properties from RTL and verification feedback (AutoSVA), improve assertion quality through retrieval-augmented reasoning, structural grounding, and guided prompting (LISA, STELLAR), combine static analysis with LLM reasoning (LASHED), and use iterative tool-in-the-loop refinement for debugging (BugWhisperer, LASHED, MEIC) (Section II-D, pp.2–3). It reports no AST-level or counterexample-driven procedure of its own. The paper’s conclusion says practical adoption depends on “grounding through executable evidence, formal methods, benchmark quality, and accelerator-aware evaluation.” (Section V, p.4).

Inference: How to apply the grounded approach, assembled by the study author from the survey’s description rather than a procedure given in the paper.

  1. Provide the LLM with scoped design documents, RTL, extracted structure, and threat/CWE records (cf. Sections II-B and II-D, pp.2–3).
  2. Ask it to state the security property in the design’s signal vocabulary and identify the relevant state transition or information flow.
  3. Generate an assertion and a test or monitor that exercises the threat scenario.
  4. Compile and run simulation or formal checks; return syntax errors, failed traces, and coverage holes for refinement.
  5. Review whether the property constrains the intended asset and whether an assumed upstream control is actually present.

Inference: In Verus, the corresponding grounding is supplying the agent with function signatures, state fields, and existing predicates; the generated artifact should be a contract plus proof function. A Verus verifier accepts only the encoded relation, so a human must audit that the relation names the right asset and attacker capability.

evidence, trust, and product threat

The survey is primarily a synthesis; its quantitative case study reports 31 transactions, 30 decoded violations, one unmapped request, and zero observed back-pressure (Section IV-D, p.4). It does not report a formal proof of NVDLA security or a denominator for all possible requests. Inference: the trusted components are the chosen public nvdlav1 RTL snapshot, the LLM-generated asset and threat tables, the SystemVerilog simulator and monitors, and the assumption that the module boundary represents the relevant security question. The authors recommend interconnect-level access control before the module, privilege or source-ID metadata, and making core_req_prdy depend on an authorization check (Table IV, p.4).

Inference: Threat to agent-written verified Rust is high when an LLM invents assets, omits caller assumptions, or generates a property that compiles but is out of scope. The strongest reusable practice is to require a scoped threat model, executable adversarial evidence, and a proof obligation tied to each asset. VL should reuse this traceability and countermeasure loop, while avoiding claims that simulation counts as universal verification.

techniques for the catalog

  • asset-to-threat modeling: enumerate protected assets, CWE mappings, attacker scenarios, objectives, and scope before writing properties
  • threat-to-test planning: turn each threat into directed transactions, coverage checks, monitors, and explicit denominators
  • grounded property generation: combine design structure, threat knowledge, and tool feedback before accepting formal assertions
  • countermeasure loop: use evidence and failed properties to propose and verify localized access-control repairs Checked 2026-10-17 against the full paper by a Claude agent (mid-paper quote: “Across all valid requests, the ready signal never deasserted, indicating zero back-pressure in the exercised cases.”): read all text of the paper (pages 1-4 plus reference list); checked every quotation, the numbers (31 transactions, 30 flagged, 29 writes and 1 read, 18-target scan, eight rapid-fire writes, Tables I-IV, CWE-1220), the section and page references, and the technique steps against the paper; changed page numbers (Section II-D quote and Table IV, Section V are on pages 2 and 4, Table I on page 3), removed the unsupported AST, counterexample-refinement and FPV claims and the human-refinement claim, replaced them with what the survey says about LISA, STELLAR, LASHED, BugWhisperer and MEIC, and marked the step lists and trust assessment as Inference; link kept from the fetch record (arXiv ID matches the paper header, arXiv:2604.01572v1); did not check the cited works themselves, and did not check the NVDLA RTL or the PDF figure beyond its text.

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